1. Field of the Invention
The present invention relates to a field-effect transistor using a Group III-V compound semiconductor, and more particularly to a high electron mobility transistor in which the impact ionization effect can be suppressed.
2. Description of the Related Art
In a high electron mobility transistor (HEMT) which is a field-effect transistor using a Group III-V compound semiconductor, an electron supply layer including a dopant is laminated with a channel layer containing no dopant, a two-dimensional electron gas is generated in the channel layer and the electrons flow in the channel layer containing no dopant so that a high-speed characteristic is obtained. Owing to this high-speed characteristic, the HEMTs have been widely used, for example, in amplifiers employed in communication systems.
In the conventional HEMTs, it was suggested to employ an In1-xGaxAs layer as the channel layer where the electrons flow, thereby further improving performance by using high electron mobility and high concentration of the two-dimensional electron gas produced in In1-xGaxAs. Such HEMTs are fabricated by laminating a layer of a Group III-V compound semiconductor lattice matched to the InP substrate surface. The composition ratio of In1-xGaxAs in this case is x=0.47. A structure in which the lattice constants of the layer laminated on a substrate is not significantly different from the lattice constants of the substrate is called a pseudomorphic structure. However, even when the lattice of the laminated crystal layer shifts from that of the substrate, when the thickness of this crystal layer is no more than the critical thickness, the crystal growth can be conducted without loosing the properties of the crystal layer. In such case, the above-mentioned composition ratio of In1-xGaxAs is not limited to x=0.47.
FIG. 5 illustrates a conventional configuration of a HEMT using the In1-xGaxAs layer as the channel layer. In such InP-type HEMT, an I-type (intrinsic:undoped) In1-yAlyAs buffer layer 102 almost lattice matched to InP, an I-type In1-xGaxAs channel layer 104, and I-type In1-yAlyAs spacer layer 105, and an N-type In1-yAlyAs electron-supplying layer 106 including a dopant such as Si are laminated on a semi-insulating InP substrate 101. An I-type In1-yAlyAs barrier layer 107 and a cap layer 108 are laminated on the electron-supplying layer 106, ohmic electrodes 109 serving as source and drain electrodes are formed on the cap layer 108, and a gate electrode 110 is formed on the barrier layer 107.
The In1-xGaxAs channel layer 104 lattice matched to InP can increase the difference in the bottom energy level of conduction band at the interface with the n-In1-yAlyAs electron-supplying layer 105 which is also lattice matched to InP, and the concentration of the two-dimensional electron gas generated in the channel layer 104 can be increased accordingly. The two-dimensional electron gas layer with a high concentration can increase the drain current and raise the current drive capability of the transistor. Furthermore, since the In1-xGaxAs channel layer 104 itself has a high electron mobility, the increase in the drain current can be made steep even in a low electric field with a low voltage between the drain and the source so that a high-speed response can be achieved.
However, a problem associated with such InP-type HEMT is that the drain resistance increases in current stress tests conducted at a high temperature. This is apparently because the In1-xGaxAs channel layer contributing to the high-speed characteristic, as described above, has a small energy band gap and, therefore, the impact ionization ratio during the application of a high electric field is increased, the electron-hole pairs generated by the impact ionization produce an excess current in the drain, and the drain resistance is degraded. The excess current caused by such impact ionization is observed as a drain conductance increase in the current-voltage characteristic of the HEMT and represents a serious problem from the standpoint of circuit design. In the I-V characteristic of the transistor, the drain conductance increase is represented by a kink.
In order to suppress such kink, a HEMT using an In1-xGaxAs1-yPy layer as a channel layer has been suggested. For example, Japanese Patent Application Laid-open No. H6-236898 disclosed a HEMT in which an In1-xGaxAs1-yPy channel layer and an In1-yAlyAs electron-supplying layer were laminated on an InP substrate. Furthermore, in order to avoid the decrease in the concentration of two-dimensional electron gas in the In1-xGaxAs1-yPy layer, it was suggested to use a two-layer channel structure composed of an In1-xGaxAs layer and an In1-xGaxAs1-yPy layer.
FIG. 6 illustrates the conventional configuration of a HEMT using the two-layer channel layer composed of In1-xGaxAs and In1-xGaxAs1-yPy. Layers identical to those shown in FIG. 5 are assigned with the same reference numbers. The difference between the HEMT shown in FIG. 6 and that shown in FIG. 5 is in that the I-type (undoped) In1-xGaxAs channel layer 104 is formed in addition to the I-type (undoped) In1-xGaxAs1-yPy channel layer 103 formed on the buffer layer 102. Thus, when the channel layer comprises an undoped In1-xGaxAs1-yPy layer and an In1-xGaxAs layer, the In1-xGaxAs is provided at the side of the electron-supplying layer 106, which has a narrow band gap and a higher difference in the energy of conduction band at the interface with the electron-supplying layer, thereby increasing the concentration of two-dimensional electron gas, and the In1-xGaxAs1-yPy layer with a low impact ionization ratio is provided at the side of the buffer layer 102.
However, in the HEMT structure shown in FIGS. 5 and 6, a separation groove from the cap layer 108 to the buffer layer 102 has to be formed for the purpose of isolation. The formation of the separation groove is usually conducted by wet etching. In this case, if the In1-xGaxAs1-yPy layer is used as the channel layer shown in FIG. 6, a wet etching process has to be used which is different from that employed for the other layers using only As as the Group V semiconductor. Generally, the compound semiconductor layer using P as the Group V semiconductor requires a wet etching process different from a wet etching process required for the compound semiconductor layer containing no P. Therefore, the element separation process employed in the fabrication of the conventional HEMT structure shown in FIG. 6 was complicated and unsuitable for actual mass production.
Furthermore, in order to lattice match the In1-xGaxAs1-yPy layer with the InP substrate, it is necessary to control the composition ratio x of the Group III element and the composition ratio y of the Group V element at the same time. In addition, the mixed crystals of the Group V are typically difficult to grow.